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numicro? nuc140 data sheet arm cortex?-m0 32-bit microcontroller publication release date: jan. 2, 2012 - 1 - revision v3.02 numicro? family nuc140 data sheet the information described in this document is the exclusive intellectual property of nuvoton technology corporation and shall not be reproduced without permission from nuvoton. nuvoton is providing this document only for reference purposes of numicro microcontroller based system design. nuvoton assumes no responsibility for errors or omissions. all data and specifications are subject to change without notice. for additional information or questions, please contact: nuvoton technology corporation.
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 2 - revision v3.02 contents 1 ? general description ......................................................................................................... 7 ? 2 ? features ................................................................................................................................. 8 ? 2.1 ? numicro ? nuc140 features ? connectivity line .......................................................... 8 ? 3 ? parts information list and pin configuration .................................................... 12 ? 3.1 ? numicro ? nuc140 products selection guide ............................................................. 12 ? 3.1.1 ? numicro ? nuc140 connectivity line selection guide ..................................................12 ? 3.2 ? pin configuration .......................................................................................................... 13 ? 3.2.1 ? numicro ? nuc140 pin diagram ....................................................................................13 ? 4 ? block diagram .................................................................................................................... 16 ? 4.1 ? numicro ? nuc140 block diagram ............................................................................... 16 ? 4.1.1 ? numicro ? nuc140 block diagram ................................................................................16 ? 5 ? functional description .................................................................................................. 17 ? 5.1 ? arm ? cortex?-m0 core .............................................................................................. 17 ? 5.2 ? system manager ........................................................................................................... 19 ? 5.2.1 ? overview ........................................................................................................................19 ? 5.2.2 ? system reset .................................................................................................................19 ? 5.2.3 ? system power distribution .............................................................................................20 ? 5.2.4 ? system memory map ......................................................................................................21 ? 5.2.5 ? system timer (systick) .................................................................................................23 ? 5.2.6 ? nested vectored interrupt controller (nvic) ..................................................................24 ? 5.3 ? clock controller ............................................................................................................ 28 ? 5.3.1 ? overview ........................................................................................................................28 ? 5.3.2 ? clock generator .............................................................................................................30 ? 5.3.3 ? system clock and systick clock ...................................................................................31 ? 5.3.4 ? peripherals clock ...........................................................................................................32 ? 5.3.5 ? power down mode clock ...............................................................................................32 ? 5.3.6 ? frequency divider output ...............................................................................................33 ? 5.4 ? usb device controller (usb) ....................................................................................... 34 ? 5.4.1 ? overview ........................................................................................................................34 ? 5.4.2 ? features .........................................................................................................................34 ? 5.5 ? general purpose i/o (gpio) ........................................................................................ 35 ? 5.5.1 ? overview ........................................................................................................................35 ? 5.5.2 ? features .........................................................................................................................35 ? 5.6 ? i 2 c serial interface controller (master/slave) (i 2 c) ...................................................... 36 ? 5.6.1 ? overview ........................................................................................................................36 ? 5.6.2 ? features .........................................................................................................................37 ? 5.7 ? pwm generator and capture timer (pwm) ................................................................ 38 ? 5.7.1 ? overview ........................................................................................................................38 ? 5.7.2 ? features .........................................................................................................................39 ? 5.8 ? real time clock (rtc) ................................................................................................. 40 ?
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 3 - revision v3.02 5.8.1 ? overview ........................................................................................................................40 ? 5.8.2 ? features .........................................................................................................................40 ? 5.9 ? serial peripheral interface (spi) ................................................................................... 41 ? 5.9.1 ? overview ........................................................................................................................41 ? 5.9.2 ? features .........................................................................................................................41 ? 5.10 ? timer controller (tmr) ................................................................................................. 42 ? 5.10.1 ? overview ......................................................................................................................42 ? 5.10.2 ? features .......................................................................................................................42 ? 5.11 ? watchdog timer (wdt) ................................................................................................ 43 ? 5.11.1 ? overview ......................................................................................................................43 ? 5.11.2 ? features .......................................................................................................................45 ? 5.12 ? uart interface controller (uart) ............................................................................... 46 ? 5.12.1 ? overview ......................................................................................................................46 ? 5.12.2 ? features .......................................................................................................................48 ? 5.13 ? controller area network (can) .................................................................................... 49 ? 5.13.1 ? overview ......................................................................................................................49 ? 5.13.2 ? features .......................................................................................................................49 ? 5.14 ? ps/2 device controller (ps2d) ..................................................................................... 50 ? 5.14.1 ? overview ......................................................................................................................50 ? 5.14.2 ? features .......................................................................................................................50 ? 5.15 ? i 2 s controller (i 2 s)......................................................................................................... 51 ? 5.15.1 ? overview ......................................................................................................................51 ? 5.15.2 ? features .......................................................................................................................51 ? 5.16 ? analog-to-digital converter (adc) ............................................................................... 52 ? 5.16.1 ? overview ......................................................................................................................52 ? 5.16.2 ? features .......................................................................................................................52 ? 5.17 ? analog comparator (cmp) ........................................................................................... 53 ? 5.17.1 ? overview ......................................................................................................................53 ? 5.17.2 ? features .......................................................................................................................53 ? 5.18 ? pdma controller (pdma) ............................................................................................. 54 ? 5.18.1 ? overview ......................................................................................................................54 ? 5.18.2 ? features .......................................................................................................................54 ? 5.19 ? external bus interface (ebi) ......................................................................................... 55 ? 5.19.1 ? overview ......................................................................................................................55 ? 5.19.2 ? features .......................................................................................................................55 ? 6 ? flash memory controller (fmc) ................................................................................ 56 ? 6.1 ? overview ....................................................................................................................... 56 ? 6.2 ? features ........................................................................................................................ 56 ? 7 ? electrical characteristics ......................................................................................... 57 ? 7.1 ? absolute maximum ratings .......................................................................................... 57 ? 7.2 ? dc electrical characteristics ........................................................................................ 58 ? 7.2.1 ? numicro ? nuc130/nuc140 dc electrical characteristics ............................................58 ?
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 4 - revision v3.02 7.3 ? ac electrical characteristics ........................................................................................ 63 ? 7.3.1 ? external 4~24 mhz high speed oscillator .....................................................................63 ? 7.3.2 ? external 4~24 mhz high speed crystal .........................................................................63 ? 7.3.3 ? external 32.768 khz low speed crystal ........................................................................64 ? 7.3.4 ? internal 22.1184 mhz high speed oscillator ..................................................................64 ? 7.3.5 ? internal 10 khz low speed oscillator .............................................................................64 ? 7.4 ? analog characteristics .................................................................................................. 65 ? 7.4.1 ? specification of 12-bit saradc .....................................................................................65 ? 7.4.2 ? specification of ldo and power management ...............................................................66 ? 7.4.3 ? specification of low voltage reset ................................................................................67 ? 7.4.4 ? specification of brown-out detector ...............................................................................67 ? 7.4.5 ? specification of power-on reset (5 v) ...........................................................................67 ? 7.4.6 ? specification of temperature sensor .............................................................................68 ? 7.4.7 ? specification of comparator ...........................................................................................68 ? 7.4.8 ? specification of usb phy ..............................................................................................69 ? 7.5 ? flash dc electrical characteristics .............................................................................. 70 ? 7.6 ? spi dynamic characteristics ........................................................................................ 71 ? 8 ? package dimensions ......................................................................................................... 73 ? 8.1 ? 100l lqfp (14x14x1.4 mm footprint 2.0mm) .............................................................. 73 ? 8.2 ? 64l lqfp (10x10x1.4mm footprint 2.0 mm) ................................................................ 74 ? 8.3 ? 48l lqfp (7x7x1.4mm footprint 2.0mm) ..................................................................... 75 ? 9 ? revision history ................................................................................................................ 76 ?
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 5 - revision v3.02 figures figure 3-1 numicro ? nuc100 series selection code ................................................................... 12 ? figure 3-5 numicro ? nuc140 lqfp 100-pin pin diagram .......................................................... 13 ? figure 3-6 numicro ? nuc140 lqfp 64-pin pin diagram ............................................................ 14 ? figure 3-7 numicro ? nuc140 lqfp 48-pin pin diagram ............................................................ 15 ? figure 4-2 numicro ? nuc140 block diagram .............................................................................. 16 ? figure 5-1 functional controller diagram ...................................................................................... 17 ? figure 5-2 numicro ? nuc140 power distribution diagram .......................................................... 20 ? figure 5-4 clock generator global view diagram ........................................................................... 29 ? figure 5-5 clock generator block diagram ..................................................................................... 30 ? figure 5-6 system clock block diagram ....................................................................................... 31 ? figure 5-7 systick clock control block diagram .......................................................................... 31 ? figure 5-8 clock source of frequency divider .............................................................................. 33 ? figure 5-9 block diagram of frequency divider ............................................................................ 33 ? figure 5-10 i 2 c bus timing ............................................................................................................ 36 ? figure 5-11 timing of interrupt and reset signal .......................................................................... 44 ? figure 7-1 typical crystal application circuit ................................................................................ 64 ? figure 7-2 spi master dynamic characteristics timing .................................................................. 72 ? figure 7-3 spi slave dynamic characteristics timing ..................................................................... 72 ?
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 6 - revision v3.02 tables table 1-1 connectivity supported table .......................................................................................... 7 ? table 5-1 address space assignments for on-chip controllers ................................................... 22 ? table 5-2 exception model ............................................................................................................ 25 ? table 5-3 system interrupt map ..................................................................................................... 26 ? table 5-4 vector table format ...................................................................................................... 27 ? table 5-5 watchdog timeout interval selection ............................................................................ 44 ? table 5-6 uart baud rate equation ............................................................................................ 46 ? table 5-7 uart baud rate setting table ..................................................................................... 47 ?
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 7 - revision v3.02 1 general description the numicro ? nuc100 series is 32-bit microcontrollers with embedded arm ? cortex?-m0 core for industrial control and applications which need rich communication interfaces. the cortex?-m0 is the newest arm ? embedded processor with 32-bit performance and at a cost equivalent to traditional 8-bit microcontroller. numicro ? nuc100 series includes nuc100, nuc120, nuc130 and nuc140 product line. the numicro ? nuc140 connectivity line with usb 2. 0 full-speed and can functions embeds cortex?-m0 core running up to 50 mhz with 32k/64k/128k-byte embedded flash, 4k/8k/16k- byte embedded sram, and 4k-byte loader rom for the isp.. it also equips with plenty of peripheral devices, such as timers, watchdog timer, rtc, pdma, uart, spi, i 2 c, i 2 s, pwm timer, gpio, lin, can, ps/2, usb 2.0 fs devi ce, 12-bit adc, analog comparator, low voltage reset controller and brown-out detector. product line uart spi i 2 c usb lin can ps/2 i 2 s nuc100 nuc120 nuc130 nuc140 table 1-1 connectivity supported table
numicro? nuc140 data sheet 2 features the equipped features are dependent on the product line and their sub products. 2.1 numicro ? nuc140 features ? connectivity line ? core C arm ? cortex?-m0 core runs up to 50 mhz C one 24-bit system timer C supports low power sleep mode C single-cycle 32-bit hardware multiplier C nvic for the 32 interrupt inputs, each with 4-levels of priority C serial wire debug supports with 2 watchpoints/4 breakpoints ? build-in ldo for wide operating voltage ranges from 2.5 v to 5.5 v ? flash memory C 32k/64k/128k bytes flash for program code C 4kb flash for isp loader C support in-system program (isp) application code update C 512 byte page erase for flash C configurable data flash address and size for 128kb system, fixed 4kb data flash for the 32kb and 64kb system C support 2 wire icp update through swd/ice interface C support fast parallel programming mode by external programmer ? sram memory C 4k/8k/16k bytes embedded sram C support pdma mode ? pdma (peripheral dma) C support 9 channels pdma for automatic dat a transfer between sram and peripherals ? clock control C flexible selection for different applications C built-in 22.1184 mhz high speed osc for system operation ? trimmed to 1 % at +25 and v dd = 5 v ? trimmed to 3 % at -40 ~ +85 and v dd = 2.5 v ~ 5.5 v C built-in 10 khz low speed osc for watchdog timer and wake-up operation C support one pll, up to 50 mhz, for high performance system operation C external 4~24 mhz high speed crystal input for usb and precise timing operation C external 32.768 khz low speed crystal input for rtc function and low power system operation ? gpio C four i/o modes: ? quasi bi-direction ? push-pull output ? open-drain output ? input only with high impendence C ttl/schmitt trigger input selectable C i/o pin can be configured as interr upt source with edge/level setting C high driver and high sink io mode support publication release date: jan. 2, 2012 - 8 - revision v3.02
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 9 - revision v3.02 ? timer C support 4 sets of 32-bit timers with 24-b it up-timer and one 8-bit pre-scale counter C independent clock source for each timer C provides one-shot, periodic, toggle an d continuous counting operation modes C support event counting function C support input capture function ? watchdog timer C multiple clock sources C 8 selectable time out period from 1.6ms ~ 26.0sec (depends on clock source) C wdt can wake-up from power down or idle mode C interrupt or reset select able on watchdog time-out ? rtc C support software compensation by setting frequency compensate register (fcr) C support rtc counter (second, minute, hour ) and calendar counter (day, month, year) C support alarm registers (second, minute, hour, day, month, year) C selectable 12-hour or 24-hour mode C automatic leap year recognition C support periodic time tick interrupt with 8 period options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second C support wake-up function ? pwm/capture C built-in up to four 16-bit pwm generator s provide eight pwm outputs or four complementary paired pwm outputs C each pwm generator equipped with one clock source selector, one clock divider, one 8-bit prescaler and one dead-zone generator for complementary paired pwm C up to eight 16-bit digital capture timers (shared with pwm timers) provide eight rising/falling capture inputs C support capture interrupt ? uart C up to three uart controllers C uart ports with flow control (txd, rxd, cts and rts) C uart0 with 64-byte fifo is for high speed C uart1/2(optional) with 16-byte fifo for standard device C support irda (sir) and lin function C support rs-485 9-bit mode and direction control. C programmable baud-rate generator up to 1/16 system clock C support pdma mode ? spi C up to four sets of spi controller C master up to 32 mhz, and slave up to 10 mhz (chip working @ 5v) C support spi master/slave mode C full duplex synchronous serial data transfer C variable length of transfer data from 1 to 32 bits C msb or lsb first data transfer C rx and tx on both rising or falling edge of serial clock independently C 2 slave/device select lines when it is as the master, and 1 slave/device select line when it is as the slave C support byte suspend mode in 32-bit transmission C support pdma mode C support three wire, no slave select signal, bi-direction interface
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 10 - revision v3.02 ? i 2 c C up to two sets of i 2 c device C master/slave mode C bidirectional data transfer between masters and slaves C multi-master bus (no central master) C arbitration between simultaneously transmitti ng masters without co rruption of serial data on the bus C serial clock synchronization allows devices with different bit rates to communicate via one serial bus C serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer C programmable clocks allow versatile rate control C support multiple address recognition (fou r slave address with mask option) ? i 2 s C interface with external audio codec C operate as either master or slave mode C capable of handling 8-, 16-, 24- and 32-bit word sizes C mono and stereo audio data supported C i 2 s and msb justified data format supported C two 8 word fifo data buffers are provided, one for transmit and one for receive C generates interrupt requests when buffer levels cross a programmable boundary C support two dma requests, one for transmit and one for receive ? can 2.0 C supports can protocol version 2.0 part a and b C bit rates up to 1m bit/s C 32 message objects C each message object has its won identifier mask C programmable fifo mode (concatenation of message object) C maskable interrupt C disabled automatic re-transmission mode for time triggered can applications C support power down wake-up function ? ps/2 device controller C host communication inhibit and request to send detection C reception frame error detection C programmable 1 to 16 bytes transmit buffer to reduce cpu intervention C double buffer for data reception C s/w override bus ? usb 2.0 full-speed device C one set of usb 2.0 fs device 12mbps C on-chip usb transceiver C provide 1 interrupt source with 4 interrupt events C support control, bulk in/out, in terrupt and isochronous transfers C auto suspend function when no bus signaling for 3 ms C provide 6 programmable endpoints C include 512 bytes internal sram as usb buffer C provide remote wake-up capability ? ebi (external bus interface) support (100-pin and 64-pin package only) C accessible space: 64kb in 8-bit mode or 128kb in 16-bit mode C support 8-/16-bit data width
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 11 - revision v3.02 C support byte write in 16-bit data width mode ? adc C 12-bit sar adc with 700k sps C up to 8-ch single-end input or 4-ch differential input C single scan/single cycle scan/continuous scan C each channel with individual result register C scan on enabled channels C threshold voltage detection C conversion start by software programming or external input C support pdma mode ? analog comparator C up to two analog comparators C external input or internal bandgap voltage selectable at negative node C interrupt when compare result change C power down wake-up ? one built-in temperature sensor with 1 resolution ? brown-out detector C with 4 levels: 4.5 v/3.8 v/2.7 v/2.2 v C support brown-out interrupt and reset option ? low voltage reset C threshold voltage levels: 2.0 v ? operating temperature: -40 ~85 ? packages: C all green package (rohs) C lqfp 100-pin / 64-pin / 48-pin
numicro? nuc140 data sheet 3 parts information list and pin configuration 3.1 numicro ? nuc140 products selection guide 3.1.1 numicro ? nuc140 connectivity line selection guide connectivity part number aprom ram data flash isp loader rom i/o timer uart spi i 2 c usb lin can i 2 s comp. pwm adc rtc ebi isp icp package nuc140lc1cn 32 kb 4 kb 4 kb 4 kb up to 31 4x32-bit 2 1 2 1 2 1 1 1 4 8x12-bit v - v lqfp48 nuc140ld2cn 64 kb 8 kb 4 kb 4 kb up to 31 4x32-bit 2 1 2 1 2 1 1 1 4 8x12-bit v - v lqfp48 nuc140le3cn 128 kb 16 kb definable 4 kb up to 31 4x32-bit 2 1 2 1 2 1 1 1 4 8x12-bit v - v lqfp48 nuc140rc1cn 32 kb 4 kb 4 kb 4 kb up to 45 4x32-bit 3 2 2 1 2 1 1 2 4 8x12-bit v v v lqfp64 nuc140rd2cn 64 kb 8 kb 4 kb 4 kb up to 45 4x32-bit 3 2 2 1 2 1 1 2 4 8x12-bit v v v lqfp64 nuc140re3cn 128 kb 16 kb definable 4 kb up to 45 4x32-bit 3 2 2 1 2 1 1 2 4 8x12-bit v v v lqfp64 NUC140VE3CN 128 kb 16 kb definable 4 kb up to 76 4x32-bit 3 4 2 1 2 1 1 2 8 8x12-bit v v v lqfp100 nuc 1 0 -xx arm-based 32-bit microcontroller 0: advance line 2: usb line 3: automotive line 4: connectivity line cpu core 1: cortex-m0 5/7: arm7 9: arm9 temperature n: -40 ~ +85 e: -40 ~ +105 c: -40 ~ +125 reserve x x function 0 package type y: qfn 36 l: lqfp 48 r: lqfp 64 v: lqfp 100 x ram size 1: 4k 2: 8k 3: 16k aprom size a: 8k b: 16k c: 32k d: 64k e: 128k figure 3-1 numicro ? nuc100 series selection code publication release date: jan. 2, 2012 - 12 - revision v3.02
numicro? nuc140 data sheet 3.2 pin configuration 3.2.1 numicro ? nuc140 pin diagram 3.2.1.1 numicro ? nuc140 lqfp 100 pin ad8/adc5/pa.5 ad7/adc6/pa.6 ad6/adc7/spiss21/pa.7 spiss31/int0/pb.14 ad1/cpo1/pb.13 ad0/clko/cpo0/ pb.12 x32i x32o nrd/i2c1scl/pa.11 nwr/i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rxd1/pb.4 txd1/pb.5 ale/rts1/pb.6 ncs/cts1/pb.7 ldo v dd v ss ad5/cpn0/pc.7 ad4/cpp0/pc.6 ad3/cpn1/pc.15 ad2/cpp1/pc.14 t0ex/int1/pb.15 xt1_out xt1_in /reset stadc/tm0/pb.8 pa.4/adc4/ad9 pa.3/adc3/ad10 pa.2/adc2/ad11 pa.1/adc1/ad12 pa.0/adc0 av ss ice_ck ice_dat pa.12/pwm0/ad13 pa.13/pwm1/ad14 pa.14/pwm2/ad15 pa.15/pwm3/i2smclk pc.8/spiss10 pc.9/spiclk1 av dd v ss v dd pv ss pc.0/spiss00/i2slrclk pc.1/spiclk0/i2sbclk pc.2/miso00/i2sdi pc.3/mosi00/i2sdo pd.15/txd2 pd.14/rxd2 pd.7/cantx0 pd.6/canrx0 pb.3/cts0/nwrh/t3ex pb.2/rts0/nwrl/t2ex pb.1/txd0 pb.0/rxd0 d+ d- v dd33 v bus 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 pc.10/miso10 pc.11/mosi10 nuc140vxxcn lqfp 100-pin 25 24 23 22 21 20 19 18 17 pe.15 pe.14 pe.13 spiss30/pd.8 spiclk3/pd.9 miso30/pd.10 mosi30/pd.11 miso31/pd.12 mosi31/pd.13 42 43 44 45 46 47 48 49 50 pe.7 pe.8 pc.4/miso01 pc.5/mosi01 pb.9/spiss11/tm1 pb.10/spiss01/tm2 pb.11/tm3/pwm4 pe.5/pwm5/t1ex pe.6 51 52 53 54 55 56 57 58 59 v ss v dd pc.12/miso11 pc.13/mosi11 pe.0/pwm6 pe.1/pwm7 pe.2 pe.3 pe.4 84 83 82 81 80 79 78 77 76 ps2dat ps2clk spiss20/pd.0 spiclk2/pd.1 miso20/pd.2 mosi20/pd.3 miso21/pd.4 mosi21/pd.5 v ref figure 3-2 numicro ? nuc140 lqfp 100-pin pin diagram publication release date: jan. 2, 2012 - 13 - revision v3.02
numicro? nuc140 data sheet 3.2.1.2 numicro ? nuc140 lqfp 64 pin ad8/adc5/pa.5 ad7/adc6/pa.6 ad6/adc7pa.7 spiss31/int0/pb.14 ad1/cpo1/pb.13 ad0/clko/cpo0/pb.12 x32i x32o nrd/i2c1scl/pa.11 nwr/i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rxd1/pb.4 txd1/pb.5 ale/rts1/pb.6 ncs/cts1/pb.7 ldo v dd v ss ad5/cpn0/pc.7 ad4/cpp0/pc.6 ad3/cpn1/pc.15 ad2/cpp1/pc.14 t0ex/int1/pb.15 xt1_out xt1_in /reset stadc/tm0/pb.8 pa.4/adc4/ad9 pa.3/adc3/ad10 pa.2/adc2/ad11 pa.1/adc1/ad12 pa.0/adc0 av ss ice_ck ice_dat pa.12/pwm0/ad13 pa.13/pwm1/ad14 pa.14/pwm2/ad15 pa.15/pwm3/i2smclk pc.8/spiss10 pc.9/spiclk1 av dd v ss v dd pv ss pc.0/spiss00/i2slrclk pc.1/spiclk0/i2sbclk pc.2/miso00/i2sdi pc.3/mosi00/i2sdo pd.15/txd2 pd.14/rxd2 pd.7/cantx0 pd.6/canrx0 pb.3/cts0/nwrh/t3ex pb.2/rts0/nwrl/t2ex pb.1/txd0 pb.0/rxd0 d+ d- v dd33 v bus 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 pc.10/miso10 pc.11/mosi10 nuc140rxxcn lqfp 64-pin figure 3-3 numicro ? nuc140 lqfp 64-pin pin diagram publication release date: jan. 2, 2012 - 14 - revision v3.02
numicro? nuc140 data sheet 3.2.1.3 numicro ? nuc140 lqfp 48 pin clko/cpo0/pb.12 x32i x32o i2c1scl/pa.11 i2c1sda/pa.10 i2c0scl/pa.9 i2c0sda/pa.8 rxd1/pb.4 txd1/pb.5 ldo v dd v ss pa.4/adc4 pa.3/adc3 pa.2/adc2 pa.1/adc1 pa.0/adc0 av ss ice_ck ice_dat pa.12/pwm0 pa.13/pwm1 pa.14/pwm2 pa.15/pwm3/i2smclk 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 figure 3-4 numicro ? nuc140 lqfp 48-pin pin diagram publication release date: jan. 2, 2012 - 15 - revision v3.02
numicro? nuc140 data sheet 4 block diagram 4.1 numicro ? nuc140 block diagram 4.1.1 numicro ? nuc140 block diagram flash 128kb cortex-m0 50mhz clk_ctl pdma isp 4kb sram 16kb gpio a,b,c,d,e uart 1 -115k i2c 1 timer 2/3 rtc wdt i2c 0 spi 0/1 uart 0 -3m pwm 0~3 timer 0/1/ 12-bit adc analog comparator por brown-out lvr peripherals with pdma i2s 10 khz 32.768 khz p l l 22.1184 mhz 4~24 mhz ldo 2.5v~ 5.5v can 0 usb-fs 512bram usbphy pwm 4~7 uart 2 -115k spi 2/3 ps2 figure 4-1 numicro ? nuc140 block diagram publication release date: jan. 2, 2012 - 16 - revision v3.02
numicro? nuc140 data sheet 5 functional description 5.1 arm ? cortex?-m0 core the cortex?-m0 processor is a configurable, mult istage, 32-bit risc processor. it has an amba ahb-lite interface and includes an nvic co mponent. it also has optional hardware debug functionality. the processor can execute thum b code and is compatible with other cortex-m profile processor. the profile supports two modes -thread mode and handler mode. handler mode is entered as a result of an exception. an exception return can only be issued in handler mode. thread mode is entered on reset, and can be entered as a result of an exception return. figure 5-1 shows the functional controller of processor. cortex-m0 processor core nested vectored interrupt controller (nvic) breakpoint and watchpoint unit debugger interface bus matrix debug access port (dap) debug cortex-m0 processor cortex-m0 components wakeup interrupt controller (wic) interrupts serial wire or jtag debug port ahb-lite interface figure 5-1 functional controller diagram the implemented device provides: sor that features: et systick timer ts little-endian data accesses dling bandoned and ption model. this is the armv6-m, z a low gate count proces ? the armv6-m thumb? instruction s ? thumb-2 technology ? armv6-m compliant 24 -bit ? a 32-bit hardware multiplier ? the system interface suppor ? the ability to have deterministic, fixed-latency, interrupt han ? load/store-multiples and multicycle-multiplies that can be a restarted to facilitate rapid interrupt handling ? c application binary interface compliant exce c application binary interface (c-abi) compliant exception model that enables the use of pure c functions as interrupt handlers publication release date: jan. 2, 2012 - 17 - revision v3.02
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 18 - revision v3.02 ? low power sleep mode entry using wait for interrupt (wfi), wait for event (wfe) instructions, or the return from interrupt sleep-on-exit feature z nvic that features: ? 32 external interrupt inputs, each with four levels of priority ? dedicated non-maskable interrupt (nmi) input. ? support for both level-sensitive and pulse-sensitive interrupt lines ? wake-up interrupt controller (wic), pr oviding ultra-low power sleep mode support. z debug support ? four hardware breakpoints. ? two watchpoints. ? program counter sampling register (pcs r) for non-intrusive code profiling. ? single step and vector catch capabilities. z bus interfaces: ? single 32-bit amba-3 ahb-lite system inte rface that provides simple integration to all system peripherals and memory. ? single 32-bit slave port that supports the dap (debug access port).
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 19 - revision v3.02 5.2 system manager 5.2.1 overview system management includes these following sections: z system resets z system memory map z system management registers for part number id, chip reset and on-chip controllers reset , multi-functional pin control z system timer (systick) z nested vectored interrupt controller (nvic) z system control registers 5.2.2 system reset the system reset can be issued by one of the below listed events. for these reset event flags can be read by rstsrc register. z the power-on reset z the low level on the /reset pin z watchdog time out reset z low voltage reset z brown-out detector reset z cpu reset z system reset system reset and power-on reset all reset the whole chip including all peripherals. the difference between system reset and power-on reset is external crystal circuit and ispcon.bs bit. system reset doesn?t reset external crystal circuit and ispcon.bs bit, but power-on reset does.
numicro? nuc140 data sheet 5.2.3 system power distribution in this chip, the power distribution is divided into three segments. z analog power from av dd and av ss provides the power for analog components operation. z digital power from v dd and v ss supplies the power to the internal regulator which provides a fixed 2.5 v power for digital operation and i/o pins. z usb transceiver power from v bus offers the power for operating the usb transceiver. the outputs of internal voltage regulators, ldo and v dd33 , require an external capacitor which should be located close to the corresponding pin. analog power (av dd ) should be the same voltage level of the digital power (v dd ). figure 5-2 shows the power distribution of numicro ? nuc140. v dd v ss x32o x32i pv ss figure 5-2 numicro ? nuc140 power distribution diagram publication release date: jan. 2, 2012 - 20 - revision v3.02
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 21 - revision v3.02 5.2.4 system memory map numicro ? nuc100 series provides 4g-byte addressi ng space. the memory locations assigned to each on-chip controllers are shown in the fo llowing table. the detailed register definition, memory space, and programming detailed will be described in the following sections for each on- chip peripherals. numicro ? nuc100 series only supports little-endian data format. address space token controllers flash and sram memory space 0x0000_0000 ? 0x0001_ffff flash_ba flash memory space (128kb) 0x2000_0000 ? 0x2000_3fff sram_ba sram memory space (16kb) 0x6000_0000 ? 0x6001_ffff extmem_ba external memory space (128kb) ahb controllers space (0x5000_0000 ? 0x501f_ffff) 0x5000_0000 ? 0x5000_01ff gcr_ba syst em global control registers 0x5000_0200 ? 0x5000_02ff clk_ba clock control registers 0x5000_0300 ? 0x5000_03ff int_ba interrupt multiplexer control registers 0x5000_4000 ? 0x5000_7fff gpio_ba gpio control registers 0x5000_8000 ? 0x5000_bfff pdma_ba peripheral dma control registers 0x5000_c000 ? 0x5000_ffff fmc_ba flash memory control registers 0x5001_0000 ? 0x5001_03ff ebi_ba external bus interface control registers apb1 controllers space (0x4000_0000 ~ 0x400f_ffff) 0x4000_4000 ? 0x4000_7fff wdt_ba wa tchdog timer control registers 0x4000_8000 ? 0x4000_bfff rtc_ba real time clock (rtc) control register 0x4001_0000 ? 0x4001_3fff tmr01_ba timer0/timer1 control registers 0x4002_0000 ? 0x4002_3fff i2c0_ba i 2 c0 interface control registers 0x4003_0000 ? 0x4003_3fff spi0_ba spi0 with master/slave function control registers 0x4003_4000 ? 0x4003_7fff spi1_ba spi1 with master/slave function control registers 0x4004_0000 ? 0x4004_3fff pwma_ba pwm0/1/2/3 control registers 0x4005_0000 ? 0x4005_3fff uart0_ba uart0 control registers 0x4006_0000 ? 0x4006_3fff usbd_ba usb 2.0 fs device controller registers
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 22 - revision v3.02 address space token controllers 0x400 d_0000 ? 0x400d_3fff acmp_ba analog comparator control registers 0x400e_0000 ? 0x400e_ffff adc_ba analog-digital-converter (adc) control registers apb2 controllers space (0x4010_0000 ~ 0x401f_ffff) 0x4010_0000 ? 0x4010_3fff ps2_ba ps/2 interface control registers 0x4011_0000 ? 0 x4011_3fff ba 3 control registers tmr23_ timer2/timer 0x4012_0000 ? 0x4012_3fff i2c 1_ba i 2 c1 interface control registers 0x4013_0000 ? 0x4013_3fff spi2_ba spi2 with master/slave function c ontrol registers 0x4013_4000 ? 0x4013_7fff spi3_ba spi3 with master/slave function control registers 0x4014_0000 ? 0x4014_3fff pwmb_ba pwm4/5/6/7 control registers 0x4015_0000 ? 0x4015_3fff uart1_ba uart1 co ntrol registers 0x4015_4000 ? 0x4015_7fff uart2_ba uart2 control registers 0x4018_0000 ? 0x4018_3fff can0_ba ters can0 bus control regis 0x401a_0000 ? 0x401a_3fff i2s_ba i 2 s interface control registers system controllers space (0xe000_e000 ~ 0xe000_efff) 0xe000_e010 ? 0xe000_e0ff scs_ba system timer control registers 0xe000_e100 ? 0xe000_ecff scs_ba external interrupt controller contr ol registers 0xe000_ed00 ? 0xe000_ed8f scs_ba system control registers table 5-1 address space assignments for on-chip controllers
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 23 - revision v3.02 5.2. the cortex-m0 includes an integrated system time r, systick. systick pr ovides a simple, 24-bit n-zer m. the counter can be used as a real time operating sy stem (rtos) tick timer or as a simple counter. ue in the systick current value e reloa systick reload value register (syst_rvr) on the nex t clock cycle, then decrement on subsequent clocks. when the l ntflag bit clears on reads. on re the register to clear it to ena will b fter it is reloaded with this value. this mechanism can be used to disable the feature independently from i ef rm ? cortex?-m0 technical 5 system timer (systick ) clear-on-write, decrementing , wr ap-o o counter with a flexible control mechanis when system timer is enabled, it will count down from the val register (syst_cvr) to z ro, and d (wrap) to the value in the counter transitions to zero, the countf ag st atus bit is set. the cou the syst_cvr value is un known set. software should write to zero before enabling the feature. t rather than an arbitrary value his ensures when it is the timer will count fr om the syst_rvr value bled. if the syst_rvr is zero, the timer e maintai ned with a current value of zero a the timer enable bit. for more detailed informat reference manual? and ?arm on, please r ? v6-m archite er to the documents ?a cture reference manual?.
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 24 - revision v3.02 t controller (nvic) ic prioritizes and handles all supported ex ceptions. all exceptions are handled in ?handler om pare the priority of t he new interrupt to the is accepted, the starting addr ess of the interrupt se rvice routine (isr) is e registers ?pc, psr, lr, r0~r3, r12? to the stack. at the end of the isr, the nvic will restore the mentioned registers from stack and resume t he normal execution. thus it will ta ke less and deterministic time to process the interrupt request. the nvic supports ?tail chaining? which handles back-to-back interrupts e fficiently without the overhead of states saving and restoration and t herefore reduces delay time in switching to pending isr at the end of current isr. the nvic al so supports ?late arrival? which improves the efficiency of concurrent isrs. when a higher prio rity interrupt request oc curs before the current isr starts to execute (at the stage of state saving and starting address fetching), the nvic will give priority to the higher one without delay penal ty. thus it advances the real-time capability. for more detailed information, please refer to the documents ?arm ? cortex?-m0 technical reference manual? and ?arm ? v6-m architecture reference manual?. 5.2.6 nested vectored interrup cortex-m0 provides an interrupt c ontroller as an integral part of the exception mode, named as ?nested vectored interrupt controller (nvic)?. it is closely coupled to the processor kernel and provides following features: z nested and vectored interrupt support z automatic processor stat e saving and restoration z reduced and deterministic interrupt latency the nv mode?. this nvic architecture su pports 32 (irq[31:0]) discrete interrupts with 4 levels of priority. all of the interrupts and most of the system exceptions can be configured to different priority levels. when an interrupt occurs, the nvic will c current running one?s priority. if the priority of t he new interrupt is higher than the current one, the new interrupt handler will override the current handler. when any interrupts fetched from a vector table in memory. there is no need to determine which interrupt is accepted and branch to the starting address of the correlat ed isr by software. while the starting address is fetched, nvic will also automatically save proc essor state including th
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 25 - revision v3.02 rity ?0? is treated as the fourth priority on ?nmi? and ?hard fault?. 5.2.6.1 exception model and system interrupt map table 5-2 lists the exception model supported by numicro ? nuc100 series. software can set four levels of priority on some of these exceptio ns as well as on all interrupts. the highest user- configurable priority is denoted as ?0? and the lowest priority is denoted as ?3?. the default priority of all the user-co n figurable interrupts is ?0?. note t hat prio the system, after three system except ions ?reset?, e xception name vector n umber priority reset 1 -3 nmi 2 -2 hard fault 3 -1 reserved 4 ~ 10 reserved svcall 11 configurable reserved 12 ~ 13 reserved pendsv 14 configurable systick 15 configurable interrupt (irq0 ~ irq31) 16 ~ 47 configurable table 5-2 exception model vector number interrupt number (bit in interrupt registers) interrupt name source ip interrupt description 0 ~ 15 - - - system exceptions 16 0 bod_out brown-out brown-out low voltage detected interrupt 17 1 wdt_int wdt watchdog timer interrupt 18 2 eint0 gpio external signal interrupt from pb.14 pin 19 3 eint1 gpio external signal interrupt from pb.15 pin 20 4 gpab_int gpio external signal interr upt from pa[15:0]/pb[13:0] 21 5 gpcde_int gpio external interrupt from pc[15:0]/pd[15:0]/pe[15:0] 22 6 pwma_int pwm0~3 pwm0, pwm1, pwm2 and pwm3 interrupt 23 7 pwmb_int pwm4~7 pwm4, pwm5, pwm6 and pwm7 interrupt 24 8 tmr0_int tmr0 timer 0 interrupt 25 9 tmr1_int tmr1 timer 1 interrupt
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 26 - revision v3.02 vector number interrupt number (bit in interrupt registers) interrupt name source ip interrupt description 26 10 tmr2_int tmr2 timer 2 interrupt 27 11 tmr3_int tmr3 timer 3 interrupt 28 12 uart02_int uart0/2 uart0 and uart2 interrupt 29 13 art1_int uart rupt u 1 uart1 inter 30 14 spi0_int spi0 spi0 interrupt 31 15 spi1_int spi1 spi1 interrupt 32 16 spi2_int spi2 spi2 interrupt 33 17 spi3_int spi3 spi3 errupt int 34 18 i2c0_int i 2 c0 i 2 nterrupt c0 i 35 19 i2c1_int i 2 c1 rrupt i 2 c1 inte 36 20 can0_int can0 can0 interrupt 37 21 reserved reserved reserved 38 erved reserved 22 res reserved 39 23 usb s device interrupt _int usbd usb 2.0 f 40 24 ps2_int ps/2 ps/2 interrupt 41 25 acmp_int acmp analog comparator-0 or comaprator-1 interrupt 42 26 p dma_int pdma pdma interrupt 43 27 i2s_int i 2 s i 2 s interrupt 44 2 pwrwu_int clkc rrupt for chip wake-up from 8 clock controller inte power down state 45 29 adc_int adc adc interrupt 46 30 reserved reserv ed reserved 47 31 rtc_int rtc real time clock interrupt table 5 -3 system interrupt map
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 27 - revision v3.02 5.2.6.2 vector table when any the processor will automatically fetch the starting address of the interrupt serv (isr) from a vector table in memory. for armv6-m, the vector table base address is fixed at 0x0000 vector table tialization value for the stack pointer on reset, and the entry point addresses for all exception handlers. the vector number on previous page defines the o tries v ciated with exception handler entry as illustrated in previo interrupts is accepted, ice routine 0000. t he contains the ini rder of en in t he ector table asso us section. ve table wo ffset ctor rd o d escription 0 s he m ck p_main ? t ain sta pointer v ector num e try p usi umber ber xception en o inter ng that vector n table 5 -4 v ab 5.2.6.3 nvic interrupts can be enabled and disabled by writing to their corresponding interrupt set- enable or interrupt clear-en er b t write-1-to-enable and write- 1-to-clear policy, both regis g abled stat e of the corresponding interrupts. when interrup ed t will cause the interrupt to become pending, however, the inter t i rupt is active when it is disabled, it remains in its active state until cleared by rese t or an exception return. clearing the enable bit prevents new activations of t nvic interrupts can be pend ded a y pair of registers to those used to enable/disable the interru d the se res tively. the registers te-1 b rs rea back the current te of the c nterrupts. the clear-pending regi as no effect on the execut status of an a . nvic interrupts are prioritized by updating an 8-bi gister (each register sup g four interrupts). the general registers associated with the nvic are m a block of memory in the system control space and w ribed xt ector t le format operation de scription able r egist it-field. he registers use a ters readin t is disabl back the , interr up current en assertion an rupt will no activate. f an inter he associated interrupt. ed/un-pen using complementar pts, name use a wri t-pe -to-en a nding register and clear-pending register le and write-1-to-clear policy, both registe pec ding ster h pended sta ion orresponding i ctive interrupt t field within a 32-bit re portin all accessibl e fro ill be desc in ne section.
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 28 - revision v3.02 ler 5.3. ets the power down enable bit (pwr_down_en) and cortex-m0 core executes the wfi instruction. after that, chip ent er power down mode and wait for wake-up interrupt source triggered to leave power down mode. in the power down mode, the c e 24 mhz high speed crystal and internal 22.1184 mhz high speed oscilla r to reduce t ption. 5.3 clock control 1 overview the clock controller generates the clocks for the whole chip, including system clocks and all peripheral clocks. the clock controller also im plements the power control function with the individually clock on/off control, clock source se lection and a clock divider. the chip will not enter power down mode until cpu s lock controller turns off th external 4~ to he ov erall system power consum
numicro? nuc140 data sheet figure 5-3 clock generator global view diagram publication release date: jan. 2, 2012 - 29 - revision v3.02
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 30 - revision v3.02 5.3.2 clock generator the clock generator consists of 5 clock sources which are listed below: z one external 32.768 khz low speed crystal z one external 4~24 mhz high speed crystal z one programmable pll fout(pll source cons ists of external 4~24 mhz high speed crystal and internal 22.1184 mhz high speed oscillator) z one internal 22.1184 mhz high speed oscillator z one internal 10 khz low speed oscillator xt_out external 4~24 mhz crystal xtl12m_en (pwrcon[0]) xt_in internal 22.1184 mhz oscillator osc22m_en (pwrcon[2]) 0 1 pll pll_src (pllcon[19]) pll fout x32o external 32.768 khz crystal 32.768 khz xtl32k_en (pwrcon[1]) x32i internal 10 khz oscillator osc10k_en(pwrcon[3]) 4~24 mhz 22.1184 mhz 10 khz figure 5-4 clock generator block diagram
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 31 - revision v3.02 ystick clock ock generator block. the (clksel0[2:0]). the block diagram is 5.3.3 system clock and s the system clock has 5 clock sources which we re generated from cl c lock source switch depends on the register hclk_s showed in figure 5-5 . 1 11 0 11 010 001 pllfout 32.768 khz 4~24 mhz 10 khz h clk_s (clksel0[2:0]) 22.1184 mhz 000 1/(hclk_n+1) hclk_n (clkdiv[3:0]) cpu in power down mode cpu ahb cpuclk hclk pclk apb figure 5-5 system clock block diagram the clock source of systick in cortex-m0 core can use cpu clock or external clock (syst_csr[2]). if using external clock, the sy stick clock (stclk) has 5 clock sources. the clock source switch depends on the setting of the register stclk_s (c lksel0[5:3]). the block diagram is showed in figure 5-6 . fig m ure 5-6 systick clock control block diagra
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 32 - revision v3.02 5.3.5 power down mode clock when chip enters into power down mode, syst em clocks, some clock sources, and some peripheral clocks will be di sabled. some cloc k sources and peripherals clock are still active in power down mode. for theses clocks which still keep active list below: z clock generator ? internal 10 khz low speed oscillator clock ? external 32.768 khz low speed crystal clock z peripherals clock (when these ip adopt ex ternal 32.768 khz low speed crystal or 10 khz low speed oscillator as clock source) 5.3.4 peripherals clock the peripherals clock had different clock source switch setting which depends on the different peripheral. please refer the clksel1 and cl ksel2 register description in 5.3.7.
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 33 - revision v3.02 utput e multiplexer is reflected to clko function pin. therefore there are 16 options of power-of-2 divided clocks with where fin is input clock frequency to the clock divider. en (frq div[4]), the chained counter starts to count. when write 0 to ntinuously runs till divided clock reaches low 5.3.6 frequency divider o this device is equipped a power-of-2 frequency divider which is composed by16 chained divide- by-2 shift registers. one of the 16 shift register outputs selected by a sixteen to on the fr equency from f in /2 1 to f in /2 16 the output formula is f out = f in /2 (n+1) , where f in is the input clock frequency, f out is the clock divider output frequency and n is the 4-bit value in fsel (frqdiv[3:0]). when write 1 to divider_ divider_en (frqdiv[4]), the c hained counter co s tate and stay in low state. figure 5-7 clock source of frequency divider figure 5-8 block diagram of frequency divider
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 34 - revision v3.02 ) 5.4. nterrupt/ usb bus which comes starting address of sram for each endpoint buffer through ?buffer segmentation register (usb_bufsegx)?. there are 6 endpoints in this controller. each of the endpoint can be configured as in or out endpoint. all the operations including control, bulk, interrupt and isochronous transfer are implemented in this block. the block of e ndpoint control is also used to manage the data sequential synchronization, endpoint states, curre nt start address, transaction status, and data buffer status for each endpoint. there are four different interrupt events in this controller. they are the wake-up function, device plug-in or plug-out event, usb events, like in ack, out ack etc, and bus events, like suspend and resume, etc. any event will cause an interrup t, and users just need to check the related event flags in interrupt event status register (usb_intsts) to acknowledge what kind of interrupt occurring, and then check the related usb endpoint status register (usb_epsts) to acknowledge what kind of event occurring in this endpoint. a software-disable function is also supported for this usb controller. it is used to simulate the disconnection of this de (usb_drvse0), the usb controller will force the output of usb_dp and usb_ dm to level low and its function is disabled. after disable the drvse0 bit, host w ill enumerate the usb device again. reference: universal serial bus specification revision 1.1 5.4.2 features this universal serial bus (usb) performs a seri al interface with a single connector type for attaching all usb peripherals to the host system. following is the feature listing of this usb. z compliant with usb 2.0 full-speed specification z provide 1 interrupt vector with 4 diffe rent interrupt events (wakeup, fldet, usb and bus) z support control/bulk/interr upt/isochronous transfer type z support suspend function when no bus activity existing for 3 ms z provide 6 endpoints for confi gurable control/bulk/interrup t/isochronous tr ansfer types and maximum 512 bytes buffer size z provide remo 5.4 us b device controller (usb 1 overview there is one set of usb 2.0 full-speed device co ntroller and transceiver in this device. it is compliant with usb 2.0 full-speed device specif ication and support control/bulk/i isochronous transfer types. in this device controller, there are two main interfaces: the apb bus and from the usb phy transceiver. for the apb bus, t he cpu can program cont rol registers through it. there are 512 bytes internal sram as data buffer in this controller. for in or out transfer, it is necessary to write data to sram or read data from sram through the apb interface or sie. users need to set the effective vice from the host. if user enables drvse0 bit te wake-up capability
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 35 - revision v3.02 , gpiod and gpioe. each port equips maximum 16 pins. each one h is about 110 k ~300 k for v dd is from 5.0 v to 2.5 5.5. on 5.5 general purpose i/o (gpio) 5.5.1 overview numicro ? nuc130/nuc140 has up to 80 general purpose i/o pins can be shared with other function pins; it depends on the chip configuration. these 80 pins are arranged in 5 ports named with gpioa, gpiob, gpioc of the 80 pins is independent and has the corresponding register bits to control the pin mode function and data. the i/o type of each of i/o pins can be configur ed by software individually as input, output, open- drain or quasi-bidirectional mode. after reset, the i/o type of all pins stay in quasi-bidirectional mode and port data register gpiox_dout[15:0] resets to 0x0000_ffff. each i/o pin equips a very weakly individual pull-up resistor whic v. 2 features z four i/o modes: ? quasi bi-directi ? push-pull output ? open-drain output ? input only with high impendence z ttl/schmitt trigger input selectable z i/o pin can be configured as inte rrupt source with edge/level setting z high driver and high sink io mode support
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 36 - revision v3.02 r (master/slave) (i 2 c) between a master and a slave synchronously to scl on the sda line on a while scl is high is interpreted as a command (start or stop). please refer to the figure 5-9 for more detail i 2 c bus timing. 5.6 i 2 c serial interface controlle 5.6.1 overview i 2 c is a two-wire, bi-directional se rial bus that provides a simple and efficient method of data exchange between devices. the i 2 c standard is a true multi-master bus including collision detection and arbitration that prevents data corrupt ion if two or more masters attempt to control the bus simultaneously. data is transferred byte-by-byte basis. each data byte is 8-bit long. there is one scl clock pulse for each data bit with the msb being transmitted first. an acknowledge bit follows each transferred byte. each bit is sampled during the high period of scl; therefore, the sda line may be changed only during the low period of scl and must be held stable during the high period of scl. a transition on the sda line figure 5-9 i c bus timing the device?s on-chip i 2 c logic provides the serial interface that meets the i 2 c bus standard mode specification. the i 2 c port handles byte transfers autonomousl y. to enable this port, the bit ens1 in i2con should be set to '1'. the i 2 c h/w interfaces to the i 2 c bus via two pins: sda and scl. pull up resistor is needed for i 2 c operation as these are open drain pins. when the i/o pins are used as i 2 c port, user must set the pins function to i 2 c in advance. 2
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 37 - revision v3.02 the i 2 c bus uses two wires (sda and scl) to transf er information between devices connected to features of the bus are: bus (no central master) z built-in a 14-bit time-out counter will request the i 2 c interrupt if the i 2 c bus hangs up and timer-out counter overflows. z external pull-up are needed for high output z programmable clocks allow versatile rate control z supports 7-bit addressing mode z i 2 c-bus controllers support multiple addre ss recognition ( four slave address with mask option) 5.6.2 features the bu s. the main z master/slave mode z bidirectional data transfer between masters and slaves z multi-master z arbitration between simultaneously transmi tting masters without corruption of serial data on the bus z serial clock synchronization allows devices with different bit rates to communicate via one serial bus z serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 38 - revision v3.02 ator and capture timer (pwm) 5.7. sets of pwm group su pports total 4 sets of pwm generators ndent pwm outputs, pwm0~pwm7, or as 4 complementary and (pwm6, pwm7) with 4 1/2, 1/4, 1/8, 1/16), two pwm timers includin cou 16-bit comparators for pwm duty control and one dead- whi en the corresponding pwm period down counter reaches zero. cycle output pwm wav form continuously. paire are determined by pwm0 timer and dead-zone of (pwm2, pwm3), (pwm4, pwm5) and timers and dead-zone generator 2, teady waveform, the 16-bit period down counter and cou registers the updated value will be load into the 16-bit down counter/ comparator at the time down counter reaching ze ro. the double buffering feature avoids glitch at pwm outputs. when the 16-bit period down counter reaches ze ro, the interrupt request is generated. if pwm- timer is set as auto-reload mode, when the down counter reaches zero, it is reloaded with pwm counter register (cnrx) automatically then start decreasing, repeatedly. if the pwm-timer is set as one-shot mode, the down count er will stop and generate one interrupt request when it reaches zero. the value of pwm counter comparator is used for pulse high width modulation. the counter control logic changes the output to high level when down-counter value matches the value of compare register. the alternate feature of the pwm-timer is digita l input capture function. if capture function is enabled the pwm output pin is switched as capture input mode. the capture0 and pwm0 share one timer which is included in pwm0 and the c apture1 and pwm1 share pwm1 timer, and etc. therefore user must setup the pwm-timer before ena ble capture feature. a fter capture feature is enabled, the capture always latched pwm-counter to capture rising latch register (crlr) when input channel has a rising transition and latched pwm-counter to capture falling latch register (cflr) when input channel has a fallin g transition. capture channel 0 interrupt is programmable by setting ccr0.crl_ie0[1 ] (rising latch interrupt enable) and ccr0.cfl_ie0[2]] (falling latch interrupt enable) to decide the condition of interrupt occur. capture channel 1 has the same feature by setting ccr0.crl_ie1[17] and ccr0.cfl_ie1[18]. and capture channel 2 to channel 3 on each group have the same feature by setting the corresponding control bits in ccr2. for each grou p, whenever capture issu es interrupt 0/1/2/3, the pwm counter 0/1/2/3 will be reload at this moment. the maximum captured frequency that pwm can c apture is confined by the capture interrupt latency. when capture interrupt occurred, software will do at l east three steps, they are: read 5.7 pwm gener 1 overview n umicro? nuc130/nuc140 has 2 which can be configured as 8 indepe p wm pairs, (pwm0, pwm1), (pwm2, pwm3), (pwm4, pwm5) p rogrammable dead-zone generators. e ach pwm generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1, g two clock selectors, two 16-bit pwm down- nters for pwm period control, two z one generator. the 4 sets of pwm generator s provide eight independent pwm interrupt flags ch are set by hardware wh e ach pwm interrupt source with its corresponding enable bit can cause cpu to request pwm interrupt. the pwm generators can be configured as one-shot mode to produce only one pwm signal or auto-reload mode to e when pcr.dzen01 is set, pwm0 and pwm1 perf orm complementary pwm paired function; the d pwm period, duty and dead-time g enerator 0. similarly, the complementary pw m pairs ( pwm6, pwm7) are controlled by pwm2, pwm4 and pwm6 4 and 6, respectively. t o prevent pwm driving output pin with uns 1 6-bit comparator are implemented with double buffer. when user writes data to nter/comparator buffer
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 39 - revision v3.02 piir to get interrupt source and read crlrx/cflr x(x=0~3) to get capture value and finally write 1 to clear piir to zero. if interrupt latency will ta ke time t0 to finish, the capture signal mustn?t imum capture frequency will be 1/t0. for pwm_clk = 25 mhz, interrupt latency is 900 ns 5.7. 5.7. 5.7. tra nsition during this interval (t0). in this ca se, the max example: hclk = 50 mhz, so the maximum capture frequency will is 1/900ns 1000 khz 2 features 2.1 pwm function features: z pwm group has two pwm generators. each pwm generator supports one 8-bit prescaler, one clock divider, two pwm-timers (down counter), one dead-zone generator and two pwm outputs. z up to 16-bit resolution z pwm interrupt request synchronized with pwm period z one-shot or auto-reload mode pwm z up to 2 pwm group (pwma/pwmb) to support 8 pwm channels or 4 pwm paired channels 2.2 capture function features: z timing control logic shar ed with pwm generators z support 8 capture input channels s hared with 8 pwm output channels z each channel supports one rising latch r egister (crlr), one falling latch register (cflr) and capture interrupt flag (capifx)
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 40 - revision v3.02 5.8 5.8. calendar message. the clock stal connected at pins x32i and x32o (reference to pin descript ions) or from an external 32.768 khz low speed oscillator output fed at pin x32i. the rtc controller provides the time message (second, minute, hour) in time r (tlr) as well as calendar mess age (day, month, year) in calendar loading sage is expressed in bcd format. it also offers alarm function that e in time alar m register (tar) and alarm calendar in calendar the rt has 8 8, 1/4, 1/2 and 1 second which are selected by r in tlr and clr is equal to alarm setting time registers tar errupt is requested if the alarm match can cause chip wake- nabled (twke (ttr[3])=1). .8.2 features d, minute, hou r) and calendar counter (day, month, year) for z day of week counter z frequency compensate register (fcr) z all time and calendar message is expressed in bcd code z support periodic time tick interrupt with 8 peri od options 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, 1/2 and 1 second z support rtc time tick and alarm match interrupt z support wake-up chip from power down mode real time clock (rtc) 1 overview real time clock (rtc) controller provides user the real time and source of rtc is from an external 32.768 khz low speed cry loadi ng registe registe r (clr). the data mes user can preset the alarm tim a larm register (car). c controller supports periodic time tick and alarm match interrupts. the periodic interrupt period options 1/128, 1/64, 1/32, 1/16, 1/ t tr (ttr[2:0]). when rtc counte a nd car, the alarm interrupt flag (riir.aif) is set and the alarm int interrupt is enabled (rier.aier=1). both rtc ti me tick and alarm u p from power down mode if wake-up function is e 5 z there i s a time counter (secon user to check the time z alarm register (second, minut e, hour, day, month, year) z 12-hour or 24-hour mode is selectable z leap year compensation automatically
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 41 - revision v3.02 ce (spi) ect 2 off-chip slave devic es at the same time. the spi controller also 5.9. z support 1-bit or 2-bit transfer mode bit length up to 32-bit of a tran sfer word and configurable word numbers up to 2 ion, so the maximum bit l ength is 64-bit for each data transfer de, but 1 device/slave select line in slave mode suspend mode r mode r mode n interface e system clock rate 5.9 serial peripheral interfa 5.9.1 overview the serial peripheral interface (spi) is a synchronous serial data communication protocol which operates in full duplex mode. devices communicate in master/slave mode with 4-wire bi-direction interface. the numicro ? nuc130/nuc140 contains up to four sets of spi controller performing a serial-to-parallel conversion on data received fr om a peripheral device, and a parallel-to-serial conversion on data transmitted to a peripheral devic e. each set of spi controller can be set as a master, it also can be configured as a slave dev ice controlled by an off-chip master device. this controller supports a variable serial clock for special application and it also supports 2-bit transfer mode to conn supports pdma function to access the data buffer. 2 features z up to four sets of spi controller z support master or slave mode operation z conf igurable of a transact z provide burst mode operation, transmit/receive can be transferred up to two times word transaction in one transfer z support msb or lsb first transfer z 2 device/slave select lines in master mo z support byte reorder function z support byte or word z variable output serial clock frequency in maste z support two programmable serial clock frequencies in maste z support two channel pdma request, one for transmitter and another for receiver z support three wire, no slave select signal, bi-directio z the spi clock rate can be configured to equal th
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 42 - revision v3.02 timer controller (tmr) ler includes four 32-bit timers , timer0~timer3, which allows user to easily 5.10 e-shot, periodic, toggle an d continuous counting operation modes r clock input) * (8-bit pre-scale counter + 1) * (24-bit tcmp) z) * (2 8 ) * (2 24 ), t is the period of timer clock dr (timer data register) 5.10 5.1 0.1 overview the ti mer control implement a timer control for applications. the timer can perform functions like frequency measurement, event counting, inte rval measurement, clock generati on, delay timing, and so on. the timer can generate an interrupt signal upon timeout, or provide the current value during operation. .2 features z 4 sets of 32-bit timers with 24-bit up-timer and one 8-bit pre-scale counter z independent clock source for each timer z prov ides on z time out period = (period of time z maximum counting cycle time = (1 / t mh z 24-bit timer value is readable through t z support event counting function to count the event from external pin z support input capture function to capture or reset counter value
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 43 - revision v3.02 imer (wdt) 5.11 18-bit free running counter with programmable time-out intervals. table 5-5 show the watchdog timeout interval selection and figure 5- 64 shows the timing of watchdog interrupt signal and reset signal. dtcr [7]) enables the watchdog ti mer and the wdt counter starts counting up. upt flag wtif will t if the watchdog timer interrupt enable bit wtie is 4 * t ) follows the time-out event. user must to avoid chip wdt last 63 wdt clocks (t rst ) trf will not be cleared he reset source. wdt also watchdog timer wake-up function enable bit (wdtr[4]) is set, if the wd t counter reaches the specific time interval defined by wtis (wdtcr [10:8]) , the chip is wake n up from power down state. first example, if wtis is set as 000, the specific time interval for chip to wake up from power down state is 2 4 * t wdt . when power down command is set by software, then, chip enters power down state. after 2 4 * t wdt time is elapsed, chip is waken up from power down state. second example, if wtis (wdtcr [10:8]) is set as 111, the specific time interval for chip to wake up from power down state is 2 18 * t wdt . if power down command is set by software, then, chip enters power down state. after 2 18 * t wdt time is elapsed, chip is waken up from power down state. notice if wtre (wdtcr [1]) is set to 1, after chip is wake n up, software should clear the watchdog timer counter by setting wtr(wdtcr [0]) to 1 as soon as possible. otherwise, if the watchdog timer counter is not cleared by setting wtr (wdtcr [0]) to 1 before time starting from waking up to software clearing watchdog timer counter is over 1024 * t wdt , the chip is reset by watchdog timer. 5.11 watchdog t .1 overview the purpose of watchdog timer is to perform a sy stem reset when system runs into an unknown state. this prevents sy stem from hanging for an infinite period of time. besides, this watchdog timer supports another function to wake-up chip from power down mode. the watchdog timer includes an setting wte (w w hen the counter reaches the selected time-out interval, watchdog timer interr b e set immediately to request a wdt interrup set, in the meanwhile, a specified delay time (102 w dt set wtr (wdtcr [0]) (watchdog timer reset) high to reset the 18-bit wdt counter f rom watchdog timer reset before the delay time expires. wtr bit is cl eared automatically by hardware after wdt counter is reset. there are eight time-out intervals with specific delay time w hich are selected by watchdog timer interval select bits wtis (wdt cr [10:8]). if the c ounter has not been cleared after the specific delay time expires, t he watchdog timer will set watchdog timer reset flag (wtrf) high and reset chip. this reset will t hen chip restarts executing pr ogram from reset vector (0x0000_0000). w b y watchdog reset. user may poll wtrf by software to recognize t provides wake-up function. when chip is powered down and the
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 44 - revision v3.02 wtis timeout interva l selection wtr timeout startinginterval interrupt period (wdt_clk=10 khz) t int t tis min. t wtr ~ max. t wtr 000 2 4 * t wdt 1024 * t wdt 1.6 ms ~ 104 ms 001 2 6 * t wdt 1024 * t wdt 6.4 ms ~ 108.8 ms 010 2 8 * t wdt 1024 * t wdt 25.6 ms ~ 128 ms 011 2 10 * t wdt 1024 * t wdt 102.4 ms ~ 204.8 ms 100 2 12 * t wdt 1024 * t wdt 409.6 ms ~ 512 ms 101 2 14 * t wdt 1024 * t wdt 1.6384 s ~ 1.7408 s 110 2 16 * t wdt 1024 * t wdt 6.5536 s ~ 6.656 s 111 2 18 * t wdt 1024 * t wdt 26.2144 s ~ 26.3168 s table 5-5 watchdog timeout interval selection t tis rst int 1024 * t wdt 63 * t wdt minimum t wtr t int t rst maximum t wtr t wdt t wdt : watchdog engine clock time period t tis : watchdog timeout interval selection period t int : watchdog interrupt period t rst : watchdog reset period t wtr : watchdog timeout interval period figure 5-10 timing of interrupt and reset signal
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 45 - revision v3.02 5.11.2 features z 18-bit free running co r to avoid chip fr om watchdog timer re e delay time expires. z selecta ime-o l (2^4 ~ e time o 4 ms ~ 26.3168 s (if wdt_clk = 10 k z reset period = (1 / 10 khz) * 63, if wdt_clk = 10 khz. unte set before th ble t ut interva 2^18) and th ut interval is 10 hz).
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 46 - revision v3.02 uart interface controller (uart) c130/nuc140 provides up to three channels of universal asynchronous ous receiver/transmitter (uart) performs a serial-to-parallel rallel-to-serial conversion on data transmitted from the cpu. the uart controller also supports irda sir function, lin master/slave mode function and rs-485 mode functions. each uart channel supports seven types of interrupts including transmitter fifo empty interrupt (int_thre), receiver threshold level reaching interrupt (int_rda), line status interrupt (parity error or framing error or break interrupt) (int_rls), receiver buffer time out interrupt (int_tout), modem/wake-up status interrupt (int_modem), buffer error interrupt (int_buf_err) and lin receiver break field detected interrupt (int_lin_rx_break). interrupts of uart0 and uart2 share the interrupt number 12 (vector number is 28); interrupt number 13 (vector number is 29) only supports uart1 interrupt. refer to nested vectored interrupt controller chapter for system interrupt map. the uart0 is built-in with a 64-byte transmitter fifo (tx_fifo) and a 64-byte receiver fifo (rx_fifo) that reduces the number of interrupts presented to the cpu and the uart1~2 are equipped 16-byte transmitter fifo (tx_fifo) and 16 -byte receiver fifo (rx_fifo). the cpu can read the status of the uart at any time during the operation. the reported status information includes the type and condition of the transfer operations being pe rformed by the uart, as well as 4 error conditions (parity error, framing error, break interrupt and buffer error) probably occur while receiving data. the uart includes a prog rammable baud rate generator that is capable of dividing clock input by divisors to produce the seri al clock that transmitter and receiver need. the baud rate equation is baud rate = uart_clk / m * [brd + 2], where m and brd are defined in baud rate divider register (ua_baud). table 5-6 lists the equations in the various conditions and table 5-7 list the uart baud rate setting table. 5.12 numicr o? nu r eceiver/transmitters (uart). uart0 supports high speed uart and uart1~2 perform normal speed uart, besides, only uart0 and uart1 support flow control function. 5 .12.1 overview the universal asynchron c onversion on data received from the periphera l, and a pa mode div_x_en div_x_one divider x brd baud rate equation 0 0 0 b a uart_clk / [16 * (a+2)] 1 1 0 b a uart_clk / [(b+1) * (a+2)] , b must >= 8 2 1 1 don?t care a uart_clk / (a+2), a must >=3 table 5-6 uart baud rate equation system clock = internal 22.1184 mhz high speed oscillator mode0 mode1 mode2 baud rate parameter register parameter register parameter register 921600 x x a=0,b=11 0x2b00_0000 a=22 0x3000_0016 460800 a=1 0x0000_0001 a=1,b=15 a=2,b=11 0x2f00_0001 0x2b00_0002 a=46 0x3000_002e
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 47 - revision v3.02 syst em clock = internal 22.1 184 mhz high speed oscillator mode0 mode1 mode2 baud rate parameter register parameter register parameter regist er 230400 a=4 0x0000_0004 a=4,b=15 a=6,b=11 0x2f00_0004 a=94 0x3000_005e 0x2b00_0006 115200 a=10 0x0000_000a a=10,b=15 a=14,b=11 0x2f00_000a 0x2b00_000e a=190 0x3000_00be 57600 a=22 0x0000_0016 a=22,b=15 a=30,b=11 0x2f00_0016 0x2b00_001e a=382 0x3000_017e 38400 a=34 0x0000_0022 a=62,b=8 a=46,b=11 a=34,b=15 0x2800_003e 0x2b00_002e 0x2f00_0022 a=574 0x3000_023e 19200 a=70 0x0000_0046 a=126,b=8 a=94,b=11 0x2800_007e 0x2b00_005e a=1150 0x3000_047e a=70,b=15 0x2f00_0046 9600 a=142 0x0000_008e a=254,b=8 a=190,b=11 a=142,b=15 0x2800_00fe 0x2b00_00be 0x2f00_008e a=2302 0x3000_08fe 4800 a=286 0x0000_011e a=510,b=8 a=382,b=11 a=286,b=15 0x2800_01fe 0x2b00_017e 0x2f00_011e a=4606 0x3000_11fe table 5-7 uart baud rate setting table t s he uart0 and uart1 controllers support auto-flow control function that uses two low-level ignals, /cts (clear-to-send) and /rts (request- to-send), to control the flow of data transfer be th vi o . enabled, the uart is not allowed to receive dat rt ber of bytes in the rx fifo equals the value of rt s_ i_ the /rts is de- asserted. the uart sends data out when uart co roller dete device. if a valid asserted /c is not det ed the u r the uart controllers also provides a ( , r must set irda_en (ua_fun_sel [1]) to enable irda function ). the sir specificatio n defines a short-range infrared asynchronous seria 8 data bits, and 1 stop bit. the maximum data rate is 115.2 kbps (half duplex ). the irda sir block contains an irda sir protocol encoder/decoder. the irda sir protocol is half-duplex onl y. so it cannot transmit and receive data at the inimum 10ms transfer delay between transmissio nted by software. the alternate function of uart controllers is lin interconnect netw ction. the lin mode is cted by setting the ua_fun_sel[1:0] to start bit and 8-bit data format with 1-bit stop bit are re ed in acco nce for numicro ? nuc100 series nothe rt olle 9-bit mode fun n, and directi o prog gpio (pb.2 for rts0 and r rts o i y e r mode is selected by setting the ua_fun_sel register to select rs -4 85 driver control is implemented using the rts control signal from an asynchronous serial port to enable the rs-485 driver. in rs-485 mode, many characterist ics of the rx and tx are same as uart. tween e uart an d external de a until the uart asse ces (ex: m de m) s /rts to external dev when auto-flow is ice. when the num tr lev (ua_fcr [19:16]), nt a cts /cts is asserted from external t controller will not send data out. ts ect serial ird sir serial infrared) function (use l transmission mode wi th one start bit, same time. the irda sir phy sical layer specifies a m n and reception. this del ay feature must be impleme (local ork) fun sele ?01?. in lin mode, one with the lin stan quir rda dard. , a r alternate function of ua contr rs is rs-485 ctio pb.6 fo on control pr mplement the vided by r function b ts pin or can ram s-485 1) t software. th 85 function. the rs-4
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 48 - revision v3.02 5.12.2 features z full duple nous communications z separate receive / transmit 64/16/16 b art0/uart1/uart2) entry fifo for data s z support hardware auto flow control/flow control fun (cts, rts) and programmable w co ig r z programmable receiver buffer trigger level z rt pro ab g r l in lly z support cts wake-up function (ua a z rt 7-b ve z uart0/uart1 can be served by the dma controller z mma ns e t t bit by z support break error, frame erro r, nsmit buffer overflow detect n z fully programmable serial-interfac ? programmable number of da , cter programma e stic detection ? programmable x, asynchro ytes (u payload ction rts flo ntrol tr ger level (uar t0 and ua t1 support) suppo gramm le baud-rate enerator fo each channe dividua rt0 and u ut detection rt1 support) function suppo it recei r buffer time o progra setting ua_tor [dly] regis ble tra mitting data d ter elay time b t ween the las stop and he next start parity error an e characteris d receive / tra functio tics ta bit, 5-, 6- ven, odd, n 7-, 8-bit chara ? bl parity bit, e o par ity or k parity bit generati on and stop bit, 1, 1.5, or 2 stop bit generation z support irda sir function mode ? support for 3-/16-bit duration for normal mode z support lin function mode ? support lin master/slave mode ? support programmable break generation function for transmitter ? support break detect function for receiver z support rs-485 function mode. ? support rs-485 9-bit mode ? support hardware or software direct enable control provided by rts pin
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 49 - revision v3.02 area network (can) error! reference source not found. ). the can core performs the physical layer, additional red. the message are stored in the ges are implemented in the iltering, the transfer of messages ling of transmission requests as well control/configure the can core and the message handler entifier mask. sage objects). n mode for time triggered can applications. s. 5.13 controller 5 .13.1 overview the c_can consists of the can core, message ram, message handler, control registers and module interface (refer c ommunication according to the can protocol ve rsion 2.0 part a and b. the bit rate can be programmed to values up to 1mbit/s. for t he connection to t ransceiver hardware is required. f or communication on a can network, individual message objects are configu objects and identifier masks fo r acceptance filtering of rece ived messages m essage ram. all functions concerning the han dling of messa m essage handler. these functions include acc eptance f between the can core and the message ram, and the hand a s the generation of the module interrupt. t he register set of the c_can can be access ed directly by the softw are through the module interface. these registers are used to a nd to access the message ram. 5 .13.2 features z supports can protocol version 2.0 part a and b. z bit rates up to 1 mbit/s. z 32 message objects. z each message object has its own id z programmable fifo mode (concatenation of mes z maskable interrupt. z disabled automatic re-transmissio z programmable loop-back mode for self-test operation. z 16-bit module interfaces to the amba apb bu z support wake-up function
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 50 - revision v3.02 mate control over communication. data sent from the host to 5.14 z programmable 1 to 16 bytes transmit buffer to reduce cpu intervention z double buffer for data reception erride bus 5.14 ps/2 device controller (ps2d) 5.14.1 overview ps/2 device controller provides basic timing c ontrol for ps/2 communication. all communication between the device and the host is managed through the clk and data pins. unlike ps/2 keyboard or mouse device controller, the re ceived/transmit code needs to be translated as meaningful code by firmware. the device controll er generates the clk signal after receiving a request to send, but host has ulti the device is read on the rising edge and data sent from device to t he host is change after rising edge. a 16 bytes fifo is used to reduce cpu inte rvention. s/w can select 1 to 16 bytes for a continuous transmission. .2 features z host communication inhibit and request to send detection z reception frame error detection z s/w ov
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 51 - revision v3.02 5.15 ing 8-, 16-, 24- and 32-bit word sizes z mono and stereo audio data supported 2 d msb justified data format supported it and one for receive n buffer levels cross a programmable boundary 5.15 i 2 s controller (i 2 s) 5.15.1 overview the i 2 s controller consists of iis protocol to inte rface with external audio codec. two 8 word deep fifo for read path and write path respectively and is capable of handling 8 ~ 32 bit word sizes. dma controller handles the dat a movement between fifo and memory. .2 features z i 2 s can operate as either master or slave z capable of handl z i s an z two 8 word fifo data buffers are provided, one for transm z generates interrupt requests whe z two dma requests, one for transmit and one for receive
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 52 - revision v3.02 onverter (adc) /d converters can be started by software and external stadc pin. uaranteed differential analog input channels ? single mode: a/d conversion is performed one time on a specified channel ? single-cycle scan mode: a/d conversion is performed o ne cycle on all specified channels with the sequence from the lo west numbered channel to the highest numbered channel ? continuous scan mode: a/d converter conti nuously performs single-cycle scan mode until software stops a/d conversion z an a/d conversion can be started by ? software write 1 to adst bit ? external pin stadc z conversion results are held in data register s for each channel with valid and overrun indicators z conversion result can be compared with spec ify value and user can select whether to generate an interrupt when conversion result is equal to the compare register setting z channel 7 supports 3 input sources: exter nal analog voltage, internal bandgap voltage, and internal temperature sensor output z support self-calibration to minimize conversion error 5.16 analog-to-digital c 5.16.1 overview numicro ? nuc100 series contains one 12-bit succ essive approximation analog-to-digital converters (sar a/d converter) with 8 i nput channels. the a/d converter supports three operation modes: single, single-cycle scan and c ontinuous scan mode. the a 5 .16.2 features z analog input voltage range: 0~v ref z 12-bit resolution and 10-bit accuracy is g z up to 8 single-end analog input channels or 4 z maximum adc clock frequency is 16 mhz z up to 700k sps conversion rate z three operating modes
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 53 - revision v3.02 analog comparator (cmp) 00 series contains two comparators. the comparators can be used in a number e end 5.17 5.17 .1 overview numicr o? nuc1 of different configurations. the comparator output is a logical one when positive input greater than negative input, otherwise the output is a zero. each comparator can be configured to cause an interrupt when the comparator output value changes. the block diagram is shown in error! reference source not found. . 5.17.2 features z analog input voltage range: 0~5.0 v z hysteresis function supported z two analog comparators with optional inte rnal reference voltage input at negativ z one interrupt vector for both comparators
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 54 - revision v3.02 mory. top the pdma operation by dis able pdma [pdmacen]. the cpu can recognize re polling or when it receives an internal pdma urce or destination address or fixed them as well. uc140 only has 1 pdma channel (channel 0). 5.18.2 l can support a unidirectional transfer z amba ahb master/slave interface compatible, for data transfer and register read/write z support source and destination address increased mode or fixed mode z hardware channel priority. dma channel 0 has the highest priority and channel 8 has the lowest priority 5.18 pdma controller (pdma) 5.18.1 overview numicro ? nuc130/nuc140 contains a peripheral direct memory access (pdma) controller that transfers data to and from memory or transfer data to and from apb devices. the pdma has nine channels of dma (peripheral-to-memory or memo ry-to-peripheral or memory-to-memory). for each pdma channel (pdma ch0~ch8), there is o ne word buffer as transfer buffer between the peripherals apb devices and me softwa re can s the completion of a pdma operatio n by softwa interrupt. the pdma controller can increase so n otice: the partial of numicro ? nuc130/n features z support nine dma channels. each channe
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 55 - revision v3.02 s interface (ebi) 5.19 rnal devi ce and this chip, ebi support address bus and 5.19 al devices with max. 64k-byte size (8-bit data width)/128k-byte (16-bit data width) z address bus and data bus multiplex mode supported to save the address pins z configurable idle cycle supported for different access condition: write command finish (w2x), read-to-read (r2r) 5.19 external bu .1 overview the numicro ? nuc130/nuc140 lqfp-64 and lqfp-100 package equips an external bus interface (ebi) for external device used. to save the connections between exte data bus multiplex mode. and, address latch enable (ale) signal supported differentiate the address and data cycle. .2 features external bus interface has the following functions: z exter n s upported z variable external bus base clock (mclk) supported z 8-bit or 16-bit data width supported z variable data access time (tacc), address latch enable time (tale) and address hold time (tahd) supported
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 56 - revision v3.02 er (fmc) pdated th rough isp procedure. in system programming data before chip power off. for 128k bytes aprom device, the ared with original 128k program memory and its start address is configurable and 4k/32k byte s aprom device, the data flash 6.2 address read access emory (aprom) b data flash with 512 bytes page erase unit 6 fl ash memory controll 6.1 ove rview numicro ? nuc100 series equips with 128/64/32k byte s on chip embedded flash for application program memory (aprom) that can be u (isp) function enables user to update program memory when chip is soldered on pcb. after chip power on, cortex-m0 cpu fetches code from aprom or ldrom decided by boot select (cbs) in config0. by the way, numicro ? nuc100 series also provides additional data flash for user, to store some application dependent data fl ash is sh defined by user application request in config1. for 6 is fixed at 4k. features z run up to 50 mhz with zero wait state for continuous z 128/64/32kb application program m z 4kb in system programming (isp) loader program memory (ldrom) z configurable or fixed 4k z programmable data flash star t address for 128k aprom device z in system program (isp) to update on chip flash
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 57 - revision v3.02 ximum ratings 7 electrical characteristics 7.1 absolute ma parameter symbol min. max unit dc p ower supply v dd ? v ss -0.3 +7.0 v inpu t voltage v in v ss -0.3 v dd +0.3 v osci llator frequency 1/t clcl 4 24 mhz ope rating temperature ta -40 +85 c storage t tst -55 +150 c emperature max imum current into v dd - 120 ma m aximum current out of v 120 ss ma maximum current sunk by ma a i/o pin 35 m aximum current sourced by a i/o pin 35 ma m aximum current sunk by total i/o pins 100 ma m aximum current sourced by total i/o pins 100 ma note: exposure to conditions bey ond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 58 - revision v3.02 electrical characteristics (v dd -v ss = c = 50 mhz unle specified. 7 .2 dc electrical characteristics 7.2.1 numicro ? nuc130/nuc140 dc 3.3 v, ta = 25 c, fos ss otherwise ) specification para meter sym. min. typ. max. unit test conditions operation voltage v dd 2.5 5.5 v dd =2.5 v ~ v up to 50 v 5.5 mhz power ground v ss av ss -0.3 v ldo output voltage v ldo -10% 2.5 +10% v dd > 2.7 v v analog operating voltage av dd 0 v dd v analog reference voltage vref 0 av dd v i dd1 51 ma enable all ip and pll, xtal=12 mhz v dd = 5.5 v@50 mhz, i dd2 25 ma v dd = 5.5 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i dd3 48 ma v dd = 3 v@50 mhz, enable all ip and pll, xtal=12 mhz operating current normal run mode @ 50 mhz i dd4 23 ma v dd = 3 v@50 mhz, disable all ip and enable pll, xtal=12 mhz i dd5 19 ma v dd = 5.5 v@12 mhz, enable all ip and disable pll, xtal=12 mhz i dd6 7 ma v dd = 5.5 v@12 mhz, disable all ip and disable pll, xtal=12 mhz operating current normal run mode @ 12 mhz i dd7 17 ma v dd = 3 v@12 mhz, enable all ip and disable pll, xtal=12 mhz
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 59 - revision v3.02 specification parameter sym. min. typ. max. unit test conditions i dd8 6 ma v dd disa = 3 v@12 mhz, ble all ip and disable pll, xtal=12 mhz i dd9 v dd = 5 enable all ip and disable pll, xtal=4 mhz 11 ma v@4 mhz, i 0 3 ma disable all ip and disable pll, tal=4 mhz dd1 v dd = 5 v@4 mhz, x i 11 10 ma v dd = 3 v@4 mhz, a and disable pll, dd en ble all ip xtal=4 mhz operating current de @ 4 mhz 2 m v dd = 3 v@4 mhz, isable all ip and disable pll, xtal=4 mhz normal run mo i dd12 .5 a d i idle1 35 ma dd = 5.5 v@50 mhz, enable all ip and pll, xtal=12 v mhz i idle2 15 ma disable all ip and enable pll, v dd =5.5 v@50 mhz, xtal=12 mhz i idle3 33 ma enable all ip and pll, xtal=12 v dd = 3 v@50 mhz, mhz operating current idle mode i idle4 13 ma disable all ip and enable pll, @ 50 mhz v dd = 3 v@50 mhz, xtal=12 mhz i idle5 10 ma enable all ip and disable pll, v dd = 5.5 v@12 mhz, xtal=12 mhz i idle6 4.5 ma disable all ip and disable pll, v dd = 5.5 v@12 mhz, xtal=12 mhz operating current idle mode i idle7 9 ma enable all ip and disable pll, @ 12 mhz v dd = 3 v@12 mhz, xtal=12 mhz
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 60 - revision v3.02 specification parameter sym. min. typ. max. unit test conditions i idle8 3.5 ma v dd = 3 v@12 mhz, disable all ip and disable pll, xtal=12 mhz i idle9 4 ma v dd = 5 v@4 mhz, enable all ip and disable pll, xtal=4 mhz i idle10 2.5 ma v dd = 5 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i idle11 3.5 ma v dd = 3 v@4 mhz, enable all ip and disable pll, xtal=4 mhz operating current idle mode @ 4 mhz i idle12 1.5 ma v dd = 3 v@4 mhz, disable all ip and disable pll, xtal=4 mhz i pw d1 , no load 12 a v dd = 5.5 v, rtc off @ disable bov function i pwd2 9 a tc off, no load @ disable bov function v dd = 3.3 v, r i pwd3 a v dd = 5.5 v, rtc run , no load @ disable bov function standby current power down mode i pwd4 a c run , no load on v dd = 3.3 v, rt @ disable bov functi input current pa, pb, pc, pd, pe (quasi-bidirectional mode) i in1 -50 -60 a v dd = 5.5 v, v in = 0 v or v in =v dd input current at /reset [1] -55 - 5 v i in2 -45 30 a v dd = 3.3 v, v in = 0.4 input leakage current pa, pb, pc, pd, pe i lk -2 - +2 a in numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 61 - revision v3.02 specification parameter sym. min. typ. max. unit test conditions input high voltage pa, pb, pc, pd, pe (schmitt input) ih2 0.7 dd dd .5 v v - v +0 v hysteresis voltage of pa~pe (schmitt input) v hy 0.2 v dd v 0 - 0 .8 v dd = 4.5 v input low voltage xt1 [*2] v il3 0 - 0.4 v v dd = 3.0 v 3.5 - v + dd 0.2 v v = 5.5 v dd input high voltage xt1 [*2] ih3 2.4 - v dd +0.2 v v dd = 3.0 v input low v oltage x32i [*2] 0 v il4 0 - .4 v input high voltage x32i [*2] v ih4 1.7 2.5 v negative going threshold (schmitt input), /reset -0 0.3 dd v ils .5 - v v positive going threshold (schmitt input), /reset 0.7 dd v dd .5 v ihs v - +0 v i sr11 -300 -370 -450 a v dd = 4.5 v, v s = 2.4 v i sr12 -50 -70 -90 a v dd = 2.7 v, v s = 2.2 v source current pa , pb, pc, ctional i sr13 -40 -60 -80 a pd, pe (quasi-bidire mode) v dd = 2.5 v, v s = 2.0 v i sr21 -20 -24 - 28 ma v dd = 4.5 v, v s = 2.4 v i 22 -4 -6 -8 ma v dd = 2.7 v, v s = 2.2 v sr source current pa, pb, pc pd, pe (push-pull mode) , i sr23 -3 -5 -7 ma v dd = 2.5 v, v s = 2.0 v i sk11 10 16 20 ma v dd = 4.5 v, v s = 0.45 v i 1 0.45 v sk12 7 0 13 ma v dd = 2.7 v, v s = sink current pa, pb, pc, pd, pe (quasi-bidirectional and push-pull mode) i sk13 6 9 12 ma v dd = 2.5 v, v s = 0.45 v brown-out voltage with bov_vl [1:0] =00b v bo2.2 2 2.1 .2 2.3 v brown-out voltage with bov_vl [1:0] =01b v 2 bo2.7 2.6 .7 2.8 v brown-out voltage with bov_vl [1:0] =10b v bo3.8 3.6 3.8 v 4.0 brown-out voltage with bov_vl [1:0] =11b v bo4.5 4 v 4.3 .5 4.7 hysteresis range of bod voltage v bh 30 - 150 m dd = 2.5 v~5.5 v v v
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 62 - revision v3.02 specification parameter sym. min. typ. max. unit test conditions bandgap voltage v bg 1.20 1.26 1 dd = 2.5 v~5.5 v .32 v v note: inp 2. crystal input is a cmos input. pe can source a transition current w they b y driven from 1 to 0. in the nsition current reaches its maximum value wh in to 2 v. 1. /reset pin is a schmitt trigger ut. 3. pins of pa, pb, pc, pd and condition of v dd =5.5 v, 5he tra hen are en v eing externall approximates
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 63 - revision v3.02 7.3 ac electrical characteristics 7.3.1 external 4~24 mhz high speed oscillator t clcl t clcx t clch t chcx t chcl note: duty cycle is 50%. symbol parameter condition min. typ. max. unit t chcx clock high time 20 - - ns t clcx clock low time 20 - - ns t clch clock rise time - - 10 ns t chcl clock fall time - - 10 ns 7.3.2 external 4~24 mhz high speed crystal parameter condition min. typ. max. unit input clock frequency external crystal 4 12 24 mhz temperature - -40 - 85 v dd - 2.5 5 5.5 v operating current 12 mhz@ v dd = 5v - 1 - ma 7.3.2.1 typical crystal application circuits crystal c1 c2 r 4 mhz ~ 24 mhz without without without
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 64 - revision v3.02 ical crystal application circuit fig ure 7-1 typ 7.3.3 external 32.768 khz low speed crystal parameter condition min. typ. max. unit input clock frequency external crystal - 32.768 - khz temperature - -40 - 85 v dd - 2.5 - 5.5 v internal 22.1184 mhz high speed oscillator 7.3.4 para meter condition min. typ. max. unit su ltage [1] - 5.5 pply vo 2.5 - v ce equency 22. 84 nter fr - - 11 - mhz +25 ; v dd =5 v -1 - +1 % cali internal o y -40 ~+85 ; =2.5 v~5.5 v -3 - +3 % brated scillator frequenc v dd operation curr ent v dd =5 v - 500 - ua 7.3. 10 khz low speed oscillator 5 internal parameter condition min. t . yp max. unit supply voltage [1] - 2.5 5.5 - v center frequency - - 10 - khz +25 ; v dd =5 v -30 - +30 % calibrated intern requency -4 +85 ; v 5.5 v - +50 % al oscillator f 0 ~ dd =2.5 v~ -50 note: internal operation voltage comes from ldo.
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 65 - revision v3.02 .4 analog characteristics 7 7.4.1 specification of 12-bit saradc symbol parameter min. typ. max. unit - resolution - - 12 bit dnl differential nonlinearity error 3 lsb - - inl integral nonlinearity error 4 lsb - - eo offset error - 1 10 lsb eg ga in error (transfer gain) - 1 1.005 - - monotonic u g aranteed fadc adc clock frequency (av dd =5v/3v) - mhz - 16/8 fs sample rate 700 k sps - - v dda supply voltage 3 - 5.5 v i dd - 0.5 - ma i dda supply current (avg.) - 1.5 - ma v ref reference voltage - v dda - v i ref reference current (avg.) - 1 - ma v in input voltage 0 - v ref v
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 66 - revision v3.02 ower management 7.4.2 specification of ldo and p param eter min. typ. max. unit note input voltage 5 5.5 ag 2.7 v v dd inp ut volt e output voltage 0% 2.5 +10% v dd > v -1 v 2.7 temperature -40 25 85 cbp 1 - resr= hm - uf 1o note 1. it is recommended that a 10u 0nf bypass capacitor a connec betw d and e closest v ss pin of the device. 2. for ensuring power stability, a 1uf or higher ca itor must be connected between ldo ss pi the device. : f or higher capacitor and a 10 re ted een v d th pac pin and the closest v n of
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 67 - revision v3.02 7.4.3 specification of low voltage reset parameter c io ondit n min. ty p. max. unit o v peration voltage - 1.7 - 5.5 quiescent current v - ua dd =5.5 v - 5 temperature - -40 25 85 temperature=25 .7 v 1 2.0 2.3 temperature=-40 - 2.4 - v threshold voltage temperature=85 - 1.6 - v hysteresis - 0 0 0 v 7.4.4 specification of brown-out detector parameter condition min. typ. max. unit operation voltage - 2.5 - 5.5 v quiescent current av dd =5.5 v - - 125 a temperature - -40 25 85 bov_vl[1:0]=11 4.3 4.5 4.7 v bov_vl [1:0]=10 3.6 3.8 4.0 v bov_vl [1:0]=01 2.6 2.7 2.8 v brown-out voltage bov_vl [1:0]=00 2.1 2.2 2.3 v hysteresis - 30 - 150 mv 7.4.5 specification of power-on reset (5 v) parameter condition min. typ. max. unit temperature - -40 25 85 reset voltage v+ - 2 - v quiescent current vin>reset voltage - 1 - na
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 68 - revision v3.02 specification of temperature sensor 7.4.6 param eter conditions min. typ. max. unit supply voltage 2.5 - 5.5 v [1] temperature -40 - 125 curre n 6.4 - 10.5 ua nt consumptio gain -1.76 v/ m offset temp=0 720 mv note: internal operation voltage comes from ldo. 7.4.7 specification of comparator parameter condition min. typ. max. unit tempe rature - -40 25 85 v dd - 2.4 3 5.5 v v dd current 20 ua@v 3 v - 20 40 ua dd = in - 5 15 put offset voltage - mv o - 0.1 - dd -0. v utput swing v 1 input common mode range 0.1 - dd -1. v - v 2 dc gain - 70 - db - propagation delay @ vdif - 200 - ns vcm=1.2 v and f=0.1 v comparison voltage 20 50 mv@vcm=0.1 v 50 mv@vcm=v dd -1.2 @10 mv for non- hysteresis 10 20 - mv mv@vcm=1 v hysteresis on w/o and w. @vcm=0.4 v -1.2 v - 10 - mv e bit control hysteresis ~ v dd wake-up time @ cinn=1.2 v - - 2 us cinp=1.3 v
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 69 - revision v3.02 7.4.8 specification of usb phy 7.4.8.1 usb dc electrical characteristics symbol parameter conditions min. typ. max. unit v ih inp ut high (driven) 2.0 v v il input low 0.8 v v di differen ut sensitivity |padp-padm| 0.2 tial inp v v cm differential common-mo range inc ge 0.8 2.5 de ludes v di ran v v se single-ended receiver threshold 0.8 2.0 v receiver hysteresis 200 mv v ol ou tput low (driven) 0 0.3 v v oh ou tput high (driven) 2.8 3.6 v v crs out s voltage put signal cros 1.3 2.0 v r pu pull-up resistor 1 1.575 .425 k ? v trm term oltage for u (rpu) 3.0 3.6 v ination v pstream port pull up z drv driv tance steady state drive* 10 er output resis ? c in pin to gnd 2 transceiver capacitance 0 pf *driver output resi esn?t in clude series resistor res tance. 7.4.8.2 usb f lectrical characte stance do is ull-speed driver e ristics symbol parameter conditions min. typ. max. unit t fr rise 20 time c =50p l 4 ns t ff fall time 20 ns c l =50p 4 t frff rise and fall time matching t 90 111.11 % frff =t fr /t ff 7.4.8.3 usb pow on er dissipati symbol parameter conditions min. typ. max. unit standb y 50 ua input mode ua i vddreg (full speed) v ddd and v ddreg supply current (steady state) output mode ua
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 70 - revision v3.02 cteristics 7.5 fl ash dc electrical chara symbol p arameter conditions min. typ. max. unit n endu enduran c ce 10000 ycles [1] t ret retention time temp ye =25 100 ar t eras e e time 20 m page eras 40 s t mas s 50 6 m mass erase time 40 0 s t prog program time 40 us 35 55 v dd supp 2.25 2.5 2.75 v [2] ly voltage i rea dd1 14 ma d current i dd2 program/eras 7 ma e current i pd 10 ua power down current 1. nu mbe is s oltage. is table is gu production. r of program/erase cycles. 2. v dd 3. th ource from chip ldo output v aranteed by design, not test in
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 71 - revision v3.02 7.6 spi dynamic characteristics symbol paramet er min. t yp. max. unit spi master m .5v ~ 5.5v, 30pf loading capacitor) ode (v dd = 4 t ds data setup ti me - 4 2 ns t dh data hold time 0 - - ns t v data output val id time 7 11 - ns spi master m ~ 3.6v, 30pf loading capacitor) ode (v dd = 3.0v t ds data setup tim e - s 5 3 n t dh data hold time 0 - - ns t v - 13 18 data output valid time ns spi slave mode (v dd capacitor) = 4.5v ~ 5.5v, 30pf loading t ds data setup time 0 - - ns t dh data hold time 2*pclk+4 - - ns t v data output valid time - 2*pclk+11 2*pclk+19 ns spi slave mode (v dd = 3.0v ~ 3.6v, 30pf loading capacitor) t ds data setup time 0 - - ns t dh data hold time 2*pclk+6 - - ns t v data output valid time - 2*pclk+19 2*pclk+25 ns
numicro? nuc140 data sheet figure 7-2 spi master dynamic characteristics timing figure 7-3 spi slave dynamic characteristics timing publication release date: jan. 2, 2012 - 72 - revision v3.02
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 73 - revision v3.02 8 package dimensions 8.1 100l lqfp (14x14x1.4 mm footprint 2.0mm) d d e e b controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 0.638 0.630 0.622 0.50 14.10 0.20 0.27 1.45 1.40 0.17 1.35 0.011 0.057 0.055 0.007 0.053 1.60 14.00 13.90 0.10 0.05 0.008 0.063 0.020 0.556 0.551 0.547 0.004 0.002 symbol min nom max max nom min dimension in inch dimension in mm a c d e h d h e l y a1 b a 2 l1 e 0.009 0.22 0.006 0.15 7 13.90 14.00 14.10 15.80 16.00 16.20 15.80 16.00 16.20 0.556 0.551 0.547 0.638 0.630 0.622 a2 a1 a l1 e c h h 1 100 l y 25 26 50 51 7 7
numicro? nuc140 data sheet 8 .2 64l lqfp (10x10x1.4mm fo publication release date: jan. 2, 2012 - 74 - revision v3.02 otprint 2.0 mm) 0 7 0 1.00 0.75 0.60 12.00 0.45 0.039 0.030 0.024 0.472 0.018 0.50 0.20 0.27 1.45 1.60 10.00 1.40 0.09 0.17 1.35 0.05 0.008 0.011 0.057 0.063 0.393 0.055 0.020 0.004 0.007 0.053 0.002 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.20 7 0.393 10.00 0.472 12.00 0.006 0.15 0.004 0.10 3.5 3.5
numicro? nuc140 data sheet 8.3 48l lqfp (7x7x1.4mm footprint 2.0mm) y seating plane d e e b a2 a1 a 1 12 48 d h e h l1 l c controlling dimension : millimeters 0.10 0 7 0 0.004 1.00 0.75 0.60 0.45 0.039 0.030 0.024 0.018 9.10 9.00 8.90 0.358 0.354 0.350 0.50 0.20 0.25 1.45 1.40 0.10 0.15 1.35 0.008 0.010 0.057 0.055 0.026 7.10 7.00 6.90 0.280 0.276 0.272 0.004 0.006 0.053 symbol min nom max max nom min dimension in inch dimension in mm a b c d e h d h e l y 0 a a l 1 1 2 e 0.008 0.006 0.15 0.20 7 0.020 0.35 0.65 0.10 0.05 0.002 0.004 0.006 0.15 9.10 9.00 8.90 0.358 0.354 0.350 7.10 7.00 6.90 0.280 0.276 0.272 0.014 37 36 25 24 13 publication release date: jan. 2, 2012 - 75 - revision v3.02
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 76 - revision v3.02 version date page/ chap. description 9 revision history v1.00 march 1, 2010 - preliminary version initial issued v1.01 april 9, 2010 ch4 modify the block diagram v1.02 may 31, 2010 7.2 add operati on current of dc characteristics v1.03 aug. 23, 2010 7.2 modify oper ation current of dc characteristics v2.00 nov. 11, 2010 - update low density and selection table v3.00 may 6, 2011 all revise from nuc140xxxan or nuc140xxxbn to nuc140xxxcn revise nuc140 selection guide revise functional description revise dc electrical characteristics v3.01 june 22, 2011 - modify temperature sensor spec revise pin description position for multi-function t2ex, t3ex, nrd, nwr update title of spi dynamic characteristics update bod spec v3.02 jan. 2, 2012 - 1. remove feature ?dynamic priority changing? for nvic 2. modify adc analog characteristic spec 3. remove spi fifo mode
numicro? nuc140 data sheet publication release date: jan. 2, 2012 - 77 - revision v3.02 important notice nuvoton products are neither intended nor warranted for usage in systems or equipment, any malfu failu which ause loss of human lif ry or severe property damage. such applications are deemed, ?insecure usage?. insecure u i implementation, atomic energy ol ai e ents, the control or operation of dynamic, brake or safety systems designed for ve hicular use, traffic signal instruments, all types o y d th p in life. all ins us ma at t third parties lay claims to oton as a of customer?s r shall indemnify the damag lia ncu d nction or re of may c e, bodily inju sage include s, but is not l mited to: equipment for surgical contr instruments, rplan or spaceship instrum f safet evices, and o er ap lications intended to support or susta ecure age shall be de customer?s risk, and in the event tha nuv es and result bilities thus i insecure usage, custome by nuvoton. rre

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